TAILIEUCHUNG - ECE 551 Digital Design And Synthesis: Lecture 10

ECE 551 Digital Design And Synthesis: Lecture 10 has many contents: Capacitance is Unavoidable, Modern Processes Are Worse, Cap to ground & Cap to neighbors, What is a Parasitic Extractor, What is Done with These Values, Post Layout Simulation, Parasitics Don’t Just Slow Down Cells, SDF Can Handle Wire RC Delay Too, Refining your ,. | ECE 551 Digital Design And Synthesis Fall ‘09 Parasitic Capacitance SDF & Back Annotation Administrative Matters Project How is it going? Time is running out This is Dec 2nd. Due in 14 to 16 days Testbench? Statemachine? Datapath? Synthesis script & post synthesis run HW6 100 pts. Meet with Vinod or Myself by end of this week (Friday Dec 4th) and show progress on design (code for testbench, statemachine, & datapath). Wednesday Dec 9th will be last class period Capacitance is Unavoidable Any two conducting geometries separated by an insulator will have capacitance between them. In digital circuits capacitances slow the circuit down. Time to charge a capacitance C to a voltage V is proportional to C. More cap Slower charge up Unavoidable & Undesireable: Any questions on why we call it parasitic capacitance? What do Our Parasitics Look Like? Wisconsin’s most prevalent No I meant on an integrated circuit Modern Processes Are Worse As technologies scaled smaller the aspect ratio of the wires changed. Typical wire is now “taller” than it is wide. As the spacing shrank the height did not shrink, or even grew to try to recoup some of the conductance lost by narrowing the line. P- Substrate SiO2 Fringe components and line to line components now dominate. Parallel plate is a small percent of the total cap. Cap to ground & Cap to neighbors 1 2 3 4 1 2 3 CTOTAL CGROUND CLINE-LINE Design Rule (m) Capacitance (pF/cm) This graph is for the middle conductor “sandwiched” between two other conductors at minimum spacing. Not only is this sidewall and fringing capacitance brining the total cap higher, but it creates a whole new noise problem called cross-talk due to the line to line capacitances. How do we Simulate this Effect? Synopsys Doesn’t Have a Clue Sad reality is wireload model is a . Might as well go ask the local fortune teller if your circuit is going to work Need to extract the value of parasitic capacitance from actual layout of the .

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 10
• ECE 551 Digital Design
• Cap to ground
• Cap to neighbors
• Post Layout Simulation
• SDF Can Handle Wire RC Delay Too