TAILIEUCHUNG - ECE 551 Digital Design And Synthesis: Lecture 8

ECE 551 Digital Design And Synthesis: Lecture 8 has many contents: For Loops & Synthesis, Generate Statements, Use of X in Synthesis, Synthesis Pitfalls, Coding for Synthesis, Administrative Matters, For Loops & Synthesis, Unnecessary Calculations, More on Loops & Synthesis, Static Loops w/o Internal Timing, Non-Static Loops with Internal Timing, Any loop with internal timing can be done as a SM, FSM Replacement for Loops, Generated Instantiation, Generate-Conditional, Synthesis Of x And z, Use of Don’t Care in Outputs, Unintentional Latches,. | ECE 551 Digital Design And Synthesis Fall ‘09 For Loops & Synthesis Generate Statements Use of X in Synthesis Synthesis Pitfalls Coding for Synthesis Administrative Matters HW4 Due HW5 Assigned (Due Friday, 11/13) Synthesize A2D with script (individual) Simulate gate level A2D (individual) Code PWM peripheral (as team) For Loops & Synthesis Can a For Loop be synthesized? reg [15:0] countmem [0:7]; integer x; always @(posedge clk) begin for (x = 0; x For Loops & Synthesis These loops are unrolled when synthesized That’s why they must be fixed in length! Loop index is type integer but it is not actually synthesized Example creates eight 16-bit incrementers. +1 16 countmem[0] 16 clk +1 16 countmem[1] 16 clk +1 16 countmem[7] 16 clk What if loop upper limit was a parameter? Unnecessary Calculations Expressions that are fixed in a for loop are replicated due to “loop unrolling.” Solution: Move fixed (unchanging) expressions outside of all loops. for (x = 0; x More on Loops & Synthesis A loop is static (data-independent) if the number of iterations is fixed at compile-time Loop Types Static without internal timing control Combinational logic Static with internal timing control (. @(posedge clk)) Sequential logic Non-static without internal timing control Not synthesizable Non-static with internal timing control (. @(posedge clk)) Sometimes synthesizable, Sequential logic Static Loops w/o Internal Timing Combinational logic results from “loop unrolling” Example always@(a) begin

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 8
• ECE 551 Digital Design
• Use of X in Synthesis
• Coding for Synthesis
• Non Static Loops with Internal Timing
• FSM Replacement for Loops