TAILIEUCHUNG - ECE 551 Digital Design And Synthesis: Lecture 2

ECE 551 Digital Design And Synthesis: Lecture 2 has many contents: Verilog Syntax, Structural Verilog, Timing in Verilog, Commenting in Verilog, Numbers in Verilog, Registers in Verilog, Vectors in Verilog, Useful System Tasks, Syntax For Structural Verilog, Hierarchy And Source Code,. | ECE 551 Digital Design And Synthesis Fall ‘09 Lecture 2 Verilog Syntax Structural Verilog Timing in Verilog Administrative Matters Readings Chapter 4 (module and port declaration, hierarchical naming and you thought chapter 3 was boring?) Chapter 5 (structural, gate primitives, delays) Tutorial sessions Today 9/9 4:30-6:00 Thursday 9/10 1:00-2:30 Homework #1 Posted and due Friday 9/18 Comments in Verilog Commenting is important In industry many other poor schmucks are going to read your code Some poor schmuck (perhaps you 4 years later) are going to have to reference your code when a customer discovers a bug. The best comments document why you are doing what you are doing, not what you are doing. Any moron who knows verilog can tell what the code is doing. Comment why (motivation/thought process) you are doing that thing. Commenting in Verilog always @(posedge clk) begin Sig_FF1 Commenting in Verilog always @(posedge clk) /******************************************** * Sig is ansynchronous and has to be double flopped * * for meta-stability reasons prior to use ************ *********************************/ begin Sig_FF1 Administrative Matters Readings Chapter 4 (module and port declaration, hierarchical naming and you thought chapter 3 was boring?) Chapter 5 (structural, gate primitives, delays) Tutorial sessions Today 9/9 4:30-6:00 Thursday 9/10 1:00-2:30 Homework #1 Posted and due Friday 9/18 Comments in Verilog Commenting is important In industry many other poor schmucks are going to read your code Some poor schmuck (perhaps you 4 years later) are going to have to reference your code when a customer discovers a bug. The best comments document why you are doing what you are doing, not what you are doing. Any moron who knows verilog can tell what the code is doing. Comment why (motivation/thought process) you are doing that thing. Commenting in Verilog always @(posedge clk) begin Sig_FF1 <= Sig // Capture value of Sig Line in FF Sig_FF2 <= Sig_FF1; // Flop Sig_FF1 to form Sig_FF2 .

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• ECE 551 Digital Design And Synthesis Lecture 2
• ECE 551 Digital Design
• Timing in Verilog
• Commenting in Verilog
• Numbers in Verilog
• Registers in Verilog
• Vectors in Verilog