TAILIEUCHUNG - ECE 551 Digital Design And Synthesis: Lecture 4

ECE 551 Digital Design And Synthesis: Lecture 4 has many contents: Behavioral Verilog, Blocking vs Non-Blocking, Simulator Mechanics part duo, Another initial Statement Example, Trigger lists (Sensitivity lists), FlipFlops (finally getting somewhere, Know your cell library, More on Blocking,. | ECE 551 Digital Design And Synthesis Fall ‘09 Behavioral Verilog always & initial blocks Coding flops if else & case statements Blocking vs Non-Blocking Simulator Mechanics part duo Administrative Matters Readings Text Chapter 7 (Behavioral Modeling) Cummings SNUG Paper (Verilog Styles that Kill) (posted on webpage) Cover HW solution for asynch reset and tran count Midterm: Wednesday 10/21/08 5:00PM-6:45PM EH ???? Behavioral Verilog initial and always form basis of all behavioral Verilog All other behavioral statements occur within these initial and always blocks cannot be nested All assignments must be to type reg initial statements start at time 0 and execute once If there are multiple initial blocks they all start at time 0 and execute independently. They may finish independently. If multiple behavioral statements are needed within the initial statement then the initial statement can be made compound with use of begin/end More on initial statements Initial statement very useful for testbenches Initial statements don’t synthesize Don’t use them in DUT Verilog (stuff you intend to synthesize) initial Blocks `timescale 1 ns / 100 fs module full_adder_tb; reg [3:0] stim; wire s, c; full_adder(sum, carry, stim[2], stim[1], stim[0]); // instantiate DUT // monitor statement is special - only needs to be made once, initial $monitor(“%t: s=%b c=%b stim=%b”, $time, s, c, stim[2:0]); // tell our simulation when to stop initial #50 $stop; initial begin // stimulus generation for (stim = 4’h0; stim Another initial Statement Example module stim() reg m,a,b,x,y; initial m = 1’b0; initial begin #5 a = 1’b1; #25 b = 1’b0; end initial begin #10 x = 1’b0; #25 y = 1’b1; end initial #50 $finish; endmodule Modelsim What events at what times will a verilog simulator produce? $finish 50 y = 1’b1 35 b = 1’b0 30 x = 1’b0 10 a =

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 4
• ECE 551 Digital Design
• Simulator Mechanics part duo
• Another initial Statement Example
• More on Blocking
• Cummings SNUG Paper