TAILIEUCHUNG - ECE 551 Digital Design And Synthesis: Lecture 1

ECE 551 Digital Design And Synthesis: Lecture 1 has many contents: Instructor Introduction, Instructor and TA Office Hours, Course Goals, Hardware Building Blocks, Course Introduction, Administrative Stuff, Introduction to Verilog,. | ECE 551 Digital Design And Synthesis Fall ‘09 Lecture 1 Instructor Introduction Course Introduction Administrative Stuff Introduction to Verilog Instructors Eric Hoffman Not a professor Have no PhD, Masters only 17+ years industry experience doing Integrated Circuit & System design 9+ years at Intel 7+ years at ZMD (Mixed signal, Analog/Digital IC’s) 1+ years as independent consultant Instructing experience: ECE555, ECE551, ECE353 Vinod Nalamalapu = TA Instructor and TA Office Hours Eric Hoffman Office = EH2359, if not there then check B555 Hours = Held in office 1st part of semester, held in B555 later. Wednesday after class (2:20-3:30) Friday after class (2:20 – 3:30) Email = erichoffman@ TA = Vinod Nalamalapu Office Hours = Held in B555 Thursday 1:00-2:30 Email = nalamalapu@ Discussion Session(s) Monday (after class) 2:15 3:15 Room 3418 Tuesday 2:30 3:30 Room 3349 OR Course Goals Provide knowledge and experience in: Digital circuit design using a HDL (Verilog) HDL simulation How to build self checking test benches Good practices in digital design verification Synthesis of dataflow and behavioral designs Basic static timing analysis concepts Optimizing hardware designs (timing, area, power) Design tools commonly used in industry Teach you to be able to “think hardware” What You Should Already Know Principles of basic digital logic design (ECE 352) Number representations (unsigned, signed, Hex & Binary) Boolean algebra Gate-level design K-Map minimization Finite State Machines Basic datapath structures (adders, shifters, SRAM) How to log in to CAE machines and use a shell Course Website eCOW2 Follow the link on: What the Website will have: Lecture Notes (I will try to stay 1 week ahead of class) Homework Assignments Tutorials Project Information Midterm Solution Course Materials Lectures Textbook Samir Palnitkar, Verilog HDL, Prentice Hall, 2003. Standards IEEE .

• Đồ họa - Thiết kế - Flash
• ECE 551 Digital Design And Synthesis Lecture 1
• Instructor and TA Office Hours
• Hardware Building Blocks
• Introduction to Verilog
• Declaring A Module
• Important HDL Features