TAILIEUCHUNG - Lecture Introduction to computing systems (from bits & gates to C & beyond): Chapter 8 - Yale N. Patt, Sanjay J. Patel

Chapter 8 - Input/Output. The main contents of this chapter include all of the following: I/O basics; input from the keyboard; output to the monitor; a more sophisticated input routine; interrupt-driven I/O; implementation of memory-mapped I/O, revisited. | Chapter 8 Input/Output Basic organization Keyboard input Monitor output Interrupts DMA I/O Basics Definitions Input transfer data from the outside world to the computer: keyboard, mouse, scanner, bar-code reader, etc. Output transfer data from the computer to the outside: monitor, printer, LED display, etc. Peripheral: any I/O device, including disks. LC-2 supports a keyboard and a monitor 8 - Device Registers I/O Interface Through a set of Device Registers: Status register (device is busy/idle/error) Data register (data to be moved to/from device) The device registers can be read/written by the CPU LC-2 KBDR: keyboard data register KBSR: keyboard status register CRTDR: monitor data register CRTST: monitor status register KBSR[15] - keyboard ready (new character available) KBDR[7:0] - character typed (ASCII) CTRSR[15] - CRT ready CTRDR[7:0] - character to be displayed (ASCII) KBSR KBDR CTRSR CTRDR LC-2 8 - Addressing Device Registers Special I/O Instructions Read or write a device register using specialized I/O instructions. Memory Mapped I/O Use existing data movement instructions (Load & Store). Map each device register to a memory address (fixed). CPU communicates with the device registers as if they were memory locations. LC-2 Uses memory mapped I/O CRTSR CRTDR KBDR KBSR xF3FC xF3FF xF401 xF400 LC-2 memory map 8 - Synchronizing CPU and I/O Problem Speed mismatch between CPU and I/O: CPU runs at > 2 GHz, all I/O is much slower. Example : Keyboard input is at irregular intervals. Need a protocol to keep CPU & KBD synchronized Handshake synchronization CPU checks the KBD Ready status bit. If set, CPU reads the data register and resets the Ready bit. Start over. Make CPU-I/O interaction seem to be synchronous 8 - Polling v/s Interrupts (Who’s driving?) Polling - CPU driving CPU checks the ready bit of status register (as per program instructions). If (KBSR[15] == 1) then load KBDR[7:0] to a register. If the I/O device is very slow, CPU is busy .

• Phần cứng
• Computing systems
• Introduction to computing systems
• Computing machines
• Computer organization
• Device registers
• I O basics
• General purpose computers
• Data types
• Decimal numbers
• Digital logic structures
• Electronic ones
• The von Neumann Model
• Instruction cycle
• Operate instructions
• Data movement instructions
• LC 2 assembly language
• Assembly language instructions
• TRAP routines
• Privileged instructions
• Stack data structure
• Interrupt I O
• LC 3 instruction set architecture
• LC 3 data path
• Problem solving
• Structured programming
• Machine architecture
• Unsigned integers
• Von Neumann machine
• Instruction set architecture