TAILIEUCHUNG - Handbook of algorithms for physical design automation part 61

Handbook of Algorithms for Physical Design Automation part 61 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 582 Handbook of Algorithms for Physical Design Automation It has been demonstrated that K can be used to trade off the cost function the merging operation and even sink initialization. In practice we can first optimize all nets that need buffering with K 1 which limits the use of scarce resources. After performing a timing analysis those nets that still have negative slack can be reoptimized with a smaller value of K . . This process of reoptimizing and gradually reducing can continue until say K . Relating Buffering Candidate Locations to Layout Environment While the previous algorithms are considering the routing tree adjustment the following algorithm focuses on buffer insertion candidate selection for congestion reduction. Van Ginneken style algorithm assumes that a set of buffer insertion candidate locations are predetermined for the given topology. The most common method for selecting insertion points is to choose them at regular intervals. Alpert and Devgan 15 show how the quality of results is affected by the degree of wire segmenting that is performed on the topology. For example Figure shows uniform segmenting for a Steiner tree with three sinks and a single blockage. For these regions for which buffer insertion is forbidden one simply avoids inserting buffer candidate locations on top of the blockage. In Figure one can find the same uniform segmenting scheme but with finer spacing. The additional buffer insertion locations could potentially improve the timing for the buffered net for additional runtime cost. In Figure one can use roughly the same number of buffer insertion candidates as in uniform segmenting but spacing them asymmetrically. The purpose is not to improve timing performance but rather to bias van Ginneken style algorithm to insert buffers in regions of the design that are more favorable such as areas with lower congestion cost. To accomplish this buffer candidate selection Ref. 18 applies a linear time

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