TAILIEUCHUNG - Handbook of algorithms for physical design automation part 91

Handbook of Algorithms for Physical Design Automation part 91 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 882 Handbook of Algorithms for Physical Design Automation microprocessors are presented to illustrate how the basic techniques described in this chapter are applied in practice. METRICS FOR CLOCK NETWORK DESIGN Unlike other signals that carry data information the clock signal in edge-triggered circuits carry timing information by the signal transitions . edges . Therefore the metrics used in clock network design are different from those for general signal net design and these are discussed in the remainder of this section. Skew Clock skew refers to the spatial variation in the arrival time of a clock transition. The clock skew between two points i and j on a chip is defined as t tj where k and tj are the clock arrival time to point i and point j respectively. The clock skew of a chip is defined as the maximum clock skew between any two clocked elements on the chip. In general clock skew forces designers to be conservative and use a longer clock period that is a lower clock frequency for the design unless both the clock network and the circuit are specially designed to take advantage of clock skew as described in Section . Therefore clock networks with zero skew are most desirable. However because of static mismatches in the clock paths and clock loads clock skew is nonzero in practice and hence skew minimization is always one of the most important objectives in clock network design. Skew can be effectively minimized in both physical design and circuit design stages. Skew minimization approaches in physical design stage are discussed in this chapter. Deskewing techniques in circuit design stage will be illustrated by several examples in Chapter 43. Jitter is another measure of the variation in the arrival time of a clock transition. Specifically it refers to the temporal variation of the clock period at a given point on the chip. Like skew it is an important metric to the quality of the clock signal because it also forces designers to be .

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