TAILIEUCHUNG - Arithmetic Circuits
Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In the next few pages we will see few of these circuits in detail. | Digital Integrated Circuits A Design Perspective Arithmetic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic January, 2003 A Generic Digital Processor Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus An Intel Microprocessor Itanium has 6 integer execution units like this Bit-Sliced Design Bit-Sliced Datapath Itanium Integer Datapath Fetzer, Orton, ISSCC’02 Adders Full-Adder The Binary Adder Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A Å B Delete = A B Can also derive expressions for S and C o based on D and P Propagate (P) = A + B Note that we will be sometimes using an alternate definition for The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit td = O(N) tadder = (N-1)tcarry + tsum Complimentary Static CMOS Full Adder 28 Transistors Inversion Property Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property A Better Structure: The Mirror Adder Mirror Adder Stick Diagram The Mirror Adder The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . The transistors connected to Ci are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal .
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