TAILIEUCHUNG - FCA- OE: Fault aware and congestion aware routing algorithm based on Odd-Even algorithm for network on chip

The Simulation results prove the FCA-OE routing algorithm can improve the average packet latency and the average packet loss rate (10%) in the presence of permanent faults compared with OE routing algorithm and it is capable to route the packets even with the faulty switches and links in network. Simulation results demonstrate that the FCA-OE routing algorithm provides less average energy consumption as compared to the Fault-Aware Dynamic Routing algorithm. | International Journal of Computer Networks and Communications Security VOL. 3, NO. 3, MARCH 2015, 83–87 Available online at: E-ISSN 2308-9830 (Online) / ISSN 2410-0595 (Print) FCA- OE: Fault-Aware and Congestion-Aware Routing Algorithm Based on Odd-Even Algorithm for Network on Chip Amin Mehranzadeh1, Mehdi Hoodgar2 and Faraz Forootan3 1, 2, 3 Department of computer, Dezful Branch, Islamic Azad University, Dezful, Iran 1 E-mail: mehranzadeh@, 2hoodgar@, 3forootan@ ABSTRACT Routing algorithms play a crucial role in design of the network on chip .Fault and congestion are two situations that effect on the packets latency and energy consumption of NoC. This paper presents a fault and a congestion aware routing algorithm called FCA-OE based on Odd-Even (OE) routing algorithm. The simulation shows the strength of the FCA-OE by comparing it with odd-even routing algorithm under different traffic patterns. The Simulation results prove the FCA-OE routing algorithm can improve the average packet latency and the average packet loss rate (10%) in the presence of permanent faults compared with OE routing algorithm and it is capable to route the packets even with the faulty switches and links in network. Simulation results demonstrate that the FCA-OE routing algorithm provides less average energy consumption as compared to the Fault-Aware Dynamic Routing algorithm. Keywords: Network-on-Chip, Routing Algorithm, Adaptive, Fault Aware, Congestion Aware. 1 INTRODUCTION The network on chip (NoC) is a layered architecture [1] has been proposed for improve performance and scalability of system on chip (SoC). Figure 1 shows an abstract view of a NOC in this architecture. As shown, each tile consists of a resource (show as R) and a switch or router (show as S). In NoC each resource is connected to the switch by a network interface and each switch is connected to the four neighboring tiles via channels and sending packets via a path .

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