TAILIEUCHUNG - ebookReuse Methodology Manual for System-on-a-Chip Designs (3rd Ed.)p2

| CHAPTER 6 Macro Synthesis Guidelines This chapter discusses strategies for developing macro synthesis scripts that enable integrators to synthesize the macro and meet timing goals. The topics include Overview of the synthesis problem Synthesis strategies for reusable macros High-performance synthesis RAM and datapath generators Coding guidelines for synthesis scripts Overview of the Synthesis Problem There are some special problems associated with the synthesis of parameterizable soft macros The macro and synthesis scripts must allow the integrator to synthesize the macro and meet timing goals in the final chip. The macro must meet timing with the integrator s gate array or standard cell library. The macro must meet timing in the integrator s specific configuration of the macro. This chapter presents a set of tools and methodologies for achieving these goals. 138 Reuse Methodology Manual The synthesis guidelines in this chapter are based on many of the same fundamental principles guiding the previous chapter. First and foremost synthesis and timing design must start at the beginning of the macro design cycle. That is Functional specifications for the macro must describe the timing area and power requirements for the design. For larger timing-critical blocks detailed technical specifications for the macro and its various subblocks must describe the timing requirements and interfaces in detail including specifications for input and output delays and loading. RTL needs to be coded from the outset to meet both the functional and the timing requirements of the design. Coding for functionality first and then fixing timing problems later causes significant delays and poor overall performance in many designs. If these fundamental guidelines are followed then synthesis is a straightforward task. Each synthesizable unit or module in the design has a timing budget. Once each module meets this timing budget the macro is sure to meet its overall timing goals. Synthesis .

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