TAILIEUCHUNG - High Level Synthesis: from Algorithm to Digital Circuit- P12

High Level Synthesis: from Algorithm to Digital Circuit- P12: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 96 M. Meredith Synthesize RTL that implements the SystemC semantics that were simulated Use the same testbench for high-level simulation and RTL simulation The design can comprise a single module or multiple cooperating modules. In the case of multiple modules the high-level SystemC simulation ensures that the modules are operating correctly individually and working together properly. This simulation validates the algorithms the protocol implementations at the interfaces and the interactions of the modules operating concurrently. The modules can then be synthesized and the resulting RTL can be verified using the same testbench that was used at the high level. This is made possible by the mixed-mode scheduling described earlier in which the algorithm is written as untimed SystemC while the interfaces are specified as cycle-accurate SystemC. Multiple testbench configurations may be constructed to verify various combinations of high-level modules and RTL modules. Cynthesizerincorporatesacompletedependencymanagementandprocessautoma-tion system that automatically generates needed cosimulation wrappers and testbench infrastructure to automate verification of multiple configurations of high-level and RTL modules without any need to customize the testbench source code itself. Conclusion This chapter has outlined the synthesizable constructs of C and SystemC supported by the Forte Design Systems in its Cynthesizer product. It has described specific techniques that can be used to encapsulate synthesizable communication protocols in C classes for maximum reuse and techniques used to automatically produce well-structured RTL for predictable timing closure. Finally some of 5 High-Level SystemC Synthesis with Forte s Cynthesizer 97 the user-visible mechanisms for controlling scheduling and the architecture of loop implementation have been discussed along with a brief discussion of verification issues automation incorporated in the Cynthesizer product. Hopefully this has .

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