TAILIEUCHUNG - Models in Hardware Testing- P4

Models in Hardware Testing- P4:Model based testing is one of the most powerful techniques for testing hardware and software moving forward to nanoscaled CMOS circuits, we observe a plethora of new defect mechanisms, which require increasing efforts in systematic fault modeling and appropriate algorithms for test generation, fault simulation and diagnosis. | 3 Models for Delay Faults 79 Fig. A scan chain CLK p IP n LP CP SE Scan in pattern I Scan out response i-1 Scan in pattern i 1 Scan out response i Fig. Timing diagram for two pattern tests using LOC test application method clock cycle is applied to capture the circuit response to the test. SE is changed to 1 and the captured response is scanned out and at the same time the next test is shifted in. For two pattern tests two methods of test application called skewed-load Savir et al. 1993 also called launch off shift LOS and broadside Savir et al. 1994 also called launch off capture LOC are used. Both methods can be regarded to have three phases. In the first phase called initialization cycle or initialization phase IP the first vector V1 of a two pattern test V1 V2 is scanned in with SE 1. The two methods differ in the next phase called the launch phase or launch cycle LP . In LOS method the second vector V2 is obtained by shifting once with SE staying at 1. Thus V2 is restricted to be a single shift of V1. In LOC test method V2 is obtained through the combinational logic of the circuit by setting SE 0. Thus in LOC also V2 is obtained as a function of V1. In the third phase called the capture cycle CP in LOS method SE is changed to 0 and the response to the test applied is captured. In LOC method SE is maintained at 0 and the response to the test is captured as for the LOS method. The timing waveforms for the two methods are shown in Figs. and . From the waveforms for the LOS method it can be 80 . Reddy Scan out response i Scan out response i-1 Fig. Timing diagram for two pattern tests using LOS test application method seen that SE has to change fast before the capture cycle. This implies that the SE net must be designed similar to a clock network since it is also distributed to all the scan cells flip-flops . In LOC method SE has to switch after the initialization cycle and this can happen as slowly as needed by for example introducing some

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