TAILIEUCHUNG - Models in Hardware Testing- P2

Models in Hardware Testing- P2:Model based testing is one of the most powerful techniques for testing hardware and software moving forward to nanoscaled CMOS circuits, we observe a plethora of new defect mechanisms, which require increasing efforts in systematic fault modeling and appropriate algorithms for test generation, fault simulation and diagnosis. | 18 J. Figueras et al. Table Experimental results showing the history effect Arumi et al. 2008a Sequence of 0s and 1s RO 100 kQ R1 R2 R3 R4 100 M2 1s R1 R2 R3 R4 100 90 d 80 d 70 d 60 d d 50 d d 40 d d 30 d d 20 d d 10 d d 0 d d d The history effect must be minimized when performing a delay test. Otherwise resistive open defects may escape the test. For this reason when a test is applied to a specific target net in order to test for a rising falling transition the net must remain at a low high logic value for a sufficient number of cycles before the initialization pattern is applied. In this way it is assured that the target node covers the maximum voltage excursion to reach its final logic state. Finally another factor is known to influence the detectability of resistive open defects . the dynamic behavior of neighboring lines coupled to the defective line. Figure shows how the largest delay was obtained when the neighboring lines underwent the opposite transition related to the defective line. In fact the effective capacitance between two nets depends on their state as well as on the skew between the transitions generated on every line. Let us assume that CNi is the capacitance between the neighboring line and the defective line when both lines are in a quiescent state. In the case of a null skew when a transition is generated in the defective line the effective capacitance between the defective line and its neighboring line Ni can be approximated as follows Sakurai 1993 0 for the same transition in Ni CNi for Ni in a quiescent state 2CNi for the opposite transition in Ni According to Eq. obtaining the largest delay caused by a resistive open defect requires maximizing the total effective capacitances between the defective line and its neighboring lines. Although usually applied to resistive opens delay considerations can also be useful for interconnect full open defects. In nanometer technologies it has been shown how in the .

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