TAILIEUCHUNG - Timing Issues

One of the key requirements of experimental control software is that it has good temporal precision. PsychoPy aims to be as precise as possible in this domain and does achieve excellent results where these are possible. To check the accuracy with which monitor frame times are recorded on your system run the timeByFrames demo from the Coder view. | Digital Integrated Circuits A Design Perspective Timing Issues Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić January 2003 Synchronous Timing Timing Definitions Latch Parameters D Clk Q D Q Clk tc-q thold PWm tsu td-q Delays can be different for rising and falling data transitions T Register Parameters D Clk Q D Q Clk tc-q thold T tsu Delays can be different for rising and falling data transitions Clock Uncertainties Sources of clock uncertainty Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking Clock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race margin Clk Clk tSK tJS Clock Skew # of registers Clk delay Insertion delay Max Clk skew Earliest occurrence of Clk edge Nominal – /2 Latest occurrence of Clk edge Nominal + /2 Positive and Negative Skew Positive Skew Launching edge arrives before the receiving edge Negative Skew Receiving edge arrives before the launching edge Timing Constraints Minimum cycle time: T - = tc-q + tsu + tlogic Worst case is when receiving edge arrives early (positive ) Timing Constraints Hold time constraint: t(c-q, cd) + t(logic, cd) > thold + Worst case is when receiving edge arrives late Race between data and clock Impact of Jitter Longest Logic Path in Edge-Triggered Systems Clk T TSU TClk-Q TLM Latest point of launching Earliest arrival of next cycle TJI + d Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: Minimum cycle time is determined by the maximum delays through the logic Tc-q + TLM + TSU Synchronous Timing Timing Definitions Latch Parameters D Clk Q D Q Clk tc-q thold PWm tsu td-q Delays can be different for rising and falling data transitions T Register Parameters D Clk Q D Q Clk tc-q thold T tsu Delays can be different for rising and falling data transitions Clock Uncertainties Sources of clock uncertainty Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) tJS Long term tJL Variation of the pulse width Important for level sensitive clocking Clock Skew and Jitter Both skew and jitter affect the effective cycle time Only skew affects the race margin Clk Clk tSK tJS Clock Skew # of registers Clk delay Insertion delay Max .

• Điện - Điện tử
• Timing Issues
• timing definitions
• latch parameters
• register parameters
• clock uncertainties
• clock skew
• Kernel timer syntax
• A kernel timer caution
• Programming syntax
• Kernel timing issues
• An introduction to the use of kernel timers
• Jiffies overflow