TAILIEUCHUNG - ARM Architecture Reference Manual- P25

ARM Architecture Reference Manual- P25: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | VFP Instructions Notes Vectors Rounding When the LEN field of the FPSCR indicates scalar mode vector length 1 FSQRTS performs just one square root operation and vec_len 1 Sd 0 Sd and Sm 0 Sm. When the LEN field indicates a vector mode vector length 1 FSQRTS might perform more than one square root operation. Addressing Mode 3 - Single-precision vectors monadic on page C5-14 describes how FSQRTS encodes the registers it uses and how vec_len Sd i and Sm i are determined. This is a fully-rounded square root operation. The FPSCR determines the rounding mode. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. C4-93 VFP Instructions FSTD 31 28 27 26 25 24 23 22 21 20 19 16 15 12 11 10 9 8 7 6 5 4 3 0 cond 110 1 U 0 0 0 Rn Dd 10 11 offset The FSTD Floating-point Store Double-precision instruction stores a double-precision register to memory. Syntax FSTD cond Dd Rn - offset 4 where cond Is the condition under which the instruction is executed. The conditions are defined in The condition field on page A3-5. If cond is omitted the AL always condition is used. Dd Specifies the source register. Rn Specifies the register holding the base address for the transfer. offset Specifies an offset to be multiplied by 4 then added to the base address if U 1 or subtracted from it if U 0 to form the actual address of the transfer. If offset is omitted it defaults to 0. Architecture version D variants only Exceptions Data Abort Operation if ConditionPassed cond then if U 1 address Rn offset 4 else address Rn - offset 4 if big-endian Memory address 4 Dd 63 32 Memory address 4 4 Dd 31 0 else Memory address 4 Dd 31 0 Memory address 4 4 Dd 63 32 C4-94 Copyright 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E VFP Instructions Notes Addressing mode This is a special case of Addressing Mode 5 - VFP load store multiple on page C5-24. Conversions An implementation using an internal format for double-precision values must convert that format back to the external .

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