TAILIEUCHUNG - A practical guide to adopting the universal verification methodology

The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys | A Practical Guide to Adopting the Universal Verification Methodology UVM Sharon Rosenberg Kathleen A Meade 92010 Cadence Design Systems Inc. All rights reserved worldwide. Published 2010. Printed in the United Stales of America. Cadence Design Systems Inc. Cadence 2655 Seely Ave. San Jose CA 95134 USA. Open SysleniC Open SyslemC Initiative OSC1 SyslcmC and SyslemC Initiative are trademarks or registered trademarks of Open SyslemC Initiative Inc. in the United States and other countries and are used with permission. Trademarks Trademarks and service marks of Cadence Design Systems Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence s trademarks contact the corporate legal department at the address shown above or call . Al other trademarks are the property of their respective holders. Restricted Permission This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication or any portion of it may result in civil and criminal penalties. Except as specified in this permission statement this publication may not be copied reproduced modified published uploaded posted transmitted or distributed in any way without prior written permission from Cadence. The information contained in this document cannot be used in the development of like products or software whether for internal or external use and shall not be used for the benefit of any other party whether or not for consideration. Disclaimer Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement Cadence does not make and expressly disclaims any representations or warranties as to the completeness accuracy or usefulness of the information contained in this document. Cadence does .

• Kĩ thuật Viễn thông
• Universal Verification Methodology
• standardized methodology
• Reuse Methodology
• Verification Language
• SystemVerilog language