TAILIEUCHUNG - A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems

 Compression of executable code in embedded microprocessor systems, used in the past mainly to reduce the memory footprint of embedded software, is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression, based on the concepts of static (using the static representation of the executable) and dynamic (using program execution traces) entropy and compare them with a state-of-the-art compression scheme, IBM’s CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome of our work is that static compression is not directly related to bus traffic reduction, yet there is a trade off between static compression and dynamic compression, ., traffic reduction. | IEEE TRANSACTIONS ON COMPUTERS VOL. 53 NO. 4 APRIL 2004 467 A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems Luca Benini Francesco Menichelli and Mauro Olivieri Member IEEE Computer Society Abstract Compression of executable code in embedded microprocessor systems used in the past mainly to reduce the memory footprint of embedded software is gaining interest for the potential reduction in memory bus traffic and power consumption. We propose three new schemes for code compression based on the concepts of static using the static representation of the executable and dynamic using program execution traces entropy and compare them with a state-of-the-art compression scheme IBM s CodePack. The proposed schemes are competitive with CodePack for static footprint compression and achieve superior results for bus traffic and energy reduction. Another interesting outcome of our work is that static compression is not directly related to bus traffic reduction yet there is a trade off between static compression and dynamic compression . traffic reduction. Index Terms Microprocessor microcomputer applications low-power design code compression. -------------------- ---------------------- 1 Introduction PROCESSOR cores find widespread usage in the vast majority of current system-on-chip SoC architectures. State-of-the-art embedded processors are based on high-performance RISC architectures with on-chip caches and memory management unit peripheral and input-output controllers. These processors and their software development tools are sometimes developed internally but they are also often purchased as intellectual-property components by system integrators from specialized core developers. RISC instruction sets are generally very regular with fixed-length instructions The most successful RISC cores on the market today have 32-bit instructions. Even though the adoption of a fixed-length instruction set eases compiler development .

• Điện - Điện tử
• Code compression
• Microcomputer applications
• Low power design
• Embedded Microprocessor Systems
• Code Compression Schemes
• Reducing Power Consumption
• Data compression
• Variable Length Bit Codings
• Huffman code
• Compress a text
• Building a Tree
• Huffman code table
• Consumption Trends
• Weight Classes
• Emissions Regulations
• Engine Technologies
• Driveline Technologies
• Power Trains