TAILIEUCHUNG - Design of a Video Game

The task of the lab is to implement a classic video game using Spartan3 FPGA on a Xess XSA-3S1000 board. Input device for the game is a PS/2 keyboard and output device is a VGA monitor. | Tallinn University of Technology Dept. of Computer Engineering Chair of Digital Systems Design Design of a Video Game Project in IAY0070 HW SW Co-design Anti Sullin 020633 IASM-21 Project supervisor Kalle Tammemae Tallinn 2006 1. Assignment The task of the lab is to implement a classic video game using Spartan3 FPGA on a Xess XSA-3S1000 board. Input device for the game is a PS 2 keyboard and output device is a VGA monitor. 2. Solution planning - the gaming platform Memory subsystem XSA-3S1000 board has SDRAM memory. It is clocked as the FPGA on 100MHz. For the project a memory controller from Xess inc is used. The controller has a 4-level pipeline. The memory is read by VGA generator inbetween there is a 8-word FIFO buffer. Under these constraints the memory has to be read at least one word per pixel drawn. When not taking into account the SDRAM refreshes and row bank changing overhead then with 640x480 60Hz VGA 25MHz dot clock the memory usage is about 25 and there is enough time for writing next frame as well. As the memory row is changed the pipeline has to be flushed and so we lose 4 clock cycles. Thus it is important to write the memory only when the read FIFO is full. The video memory is composed of two layers. The data of both layers has to be interleaved in video memory otherwise we have to change memory row twice per pixel and we would not meet the timing restrictions. A two-port unit is used to interface the memory to VGA generator and microcontroller code at once. This multiplexes the access from both channels. The microcontroller has always lower priority to avoid starvation in VGA generator. Interfacing memory and PicoBlaze microcontroller To interface memory subsystem and PicoBlaze a memory interface is implemented. The module is on the microcontroller bus and uses 6 output ports and 3 input ports for communication. address name 7 6 5 4 3 2 1 0 000 ADDR0 A7 A6 A5 A4 A3 A2 A1 A0 001 ADDR1 A15 A14 A13 A12 A11 A10 A9 A8 010 ADDR2 A23 A22 A21 A20

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