TAILIEUCHUNG - Báo cáo " Using high algebra to design frequency divider include hazard "

Normally the frequency divider designed by Boole algebra and to design a frequency divider with any divide factor, we have to repeat all over again every design step as the same. So to avoid of wasting time and money, instead of using traditional Boole algebra in digital technical we replace it by mathematical models in high algebra. And because of that we can design frequency dividers use computer. 1. Modeling of function circuit | VNU Journal of Science Mathematics - Physics 24 2008 163-170 Using high algebra to design frequency divider include hazard Nguyen Quy Thuong VNU 144 Xuan Thuy Cau Giay Hanoi Vietnam Received 8 July 2008 received in revised form 8 August 2008 Abstract. Normally the frequency divider designed by Boole algebra and to design a frequency divider with any divide factor we have to repeat all over again every design step as the same. So to avoid of wasting time and money instead of using traditional Boole algebra in digital technical we replace it by mathematical models in high algebra. And because of that we can design frequency dividers use computer. 1. Modeling of function circuit Follow 1 2 show that with one frequency divider has 4 3 factor we need 2 flip flop FF and NAND gates to control chain so that with 4 input impulse we just have only 3 output impulse. However using NAND gate to control output impulse likes this it just right in some cases. So to design frequency divider with any divider K factor meaning with any input and output impulse follow request of user we use OR gate to control output impulse. Investigate for example the input static D and output static Q of D FF in asynchronous Divider real binary 3 input divide factor K 7 6 Fig 1. Diagram impulse of frequency divider 7 6. Fig. 2. Frequency divider 7 6 execute follow diagram impulse Fig. 1. E-mail thuongnq@ 163 164 . Thuong VNU Journal of Science Mathematics - Physics 24 2008 163-170 From circuit of frequency divider picture 2 and impulse diagram Fig. 1 we realize that in the time of first impulse to sixth impulse have at lease one of three input signal of NAND gate G1 receive 0 so output of G3 G1 G2 1. In this time frequency divider will receive 6 impulses from output gate G4. To impulse 7 output of gate G2 Q1 Q2 Q3 receive level 0 and because of that G3 0 follow G4 receive level 0 too. So because of OR gate G2 we controlled output frequency divider is M 6. From Fig. 2 we have circuit .

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