TAILIEUCHUNG - SystemVerilog For Design phần 4

đóng gói các đoàn thể công đoàn chỉ các cửa hàng một giá trị duy nhất, bất kể có bao nhiêu loại có thể được đại diện trong đoàn. Để thực hiện lưu trữ của một công đoàn trong phần cứng tổng hợp, tất cả các thành viên của liên hiệp phải được lưu trữ như là cùng một vec- | Chapter 5 SystemVerilog Arrays Structures and Unions 111 NOTE J permit reading from the same union member that matches the member of the last tagged expression written into the union. union tagged packed logic 15 0 short_word logic 31 0 word logic 63 0 long_word data_word Synthesis guidelines Only packed unions are synthesizable. packed unions A union only stores a single value regardless of how many type can be representations are in the union. To realize the storage of a union in synthesized hardware all members of the union must be stored as the same vector size using the same bit alignment. Packed unions represent the storage of a union in this way and are synthesizable. An unpacked union does not guarantee that each type will be stored in the same way and is therefore not synthesizable. Packed tagged unions are intended to be synthesizable but at the time this book was written were not widely supported by synthesis compilers. An example of using structures and unions Structures provide a mechanism to group related data together under a common name. Each piece of data can be referenced individually by name or the entire group can be referenced as a whole. Unions allow one piece of storage to be used in multiple ways. The following example models a simple Arithmetic Logic Unit that can operate on either signed or unsigned values. The ALU opcode the two operands and a flag to indicate if the operation data is signed or unsigned are passed into the ALU as a single instruction word represented as a structure. The ALU can operate on either signed values or unsigned values but not both at the same time. Therefore the signed and unsigned values are modeled as a union of two types. This allows one variable to represent both signed and unsigned values. 112 SystemVerilog for Design Chapter 11 presents another example of using structures and unions to represent complex information in a simple and intuitive form. Example 5-1 Using structures and unions package

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