TAILIEUCHUNG - Model-Based Design for Embedded Systems- P71

Model-Based Design for Embedded Systems- P71: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 686 Model-Based Design for Embedded Systems X Now 8000000 pa 00 00 00 00 XX XX XX XX X XXX 0 0 1 0 0 0 rst clk Configuration control M f n s sa z I D valid iond en clk_gel pattern sel Input from Fiber circuits input_0 input_1 input_2 input_3 Output from Fiber circuits output_0 output_1 r- output_2 output_3 FIGURE FIG test system block diagram Areas in the digital domain are executed in ModelSim while areas in the analog and optical domains are executed in Chatoyant. 00 00 00 00 it . 2 3 4 5 6 7 8 9 A E 1 C D E ÂF . I--X 977 i xi Bin III 101 03 hi niii in nui J 03 II 03 401 03 03 03 FIGURE SPOT system block diagram showing the digital data entering in parallel to the UTSI transceiver chip serialized transmitted over free-space optics deserialized with clock-recovery back into parallel data. Courtesy of 52 . propagated light back into analog signals at which point the analog circuits amplify and feed the de-serializing logic in the digital domain. Figure shows the system block diagram. CAD Tools for Multi-Domain Systems on Chips 687 SPOT tests the ability of the co-simulation environment to work with a global clock signal. This clock signal generated by the digital domain is transmitted with the data and thus crosses the co-simulation interface. This means that there are a large number of periodic events occurring. This illustrates the simulation behavior of a synchronous system versus an asynchronous system in the co-simulation environment. Given these two systems we next show the results of runtimes and event traffic for different time resolutions of the SYNC_PULSE parameter. A total of four resolutions were tested 1 ps 10 ps 100 ps and 1 ns. These values were chosen since the systems run at relatively high frequencies in the range of nanoseconds for both data bit rate and clock speed. All simulations were performed on a Dual MHz Intel Xeon Processor Dell Precision with 3 GBs of RAM running Red Hat Linux kernel version . .

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