TAILIEUCHUNG - Model-Based Design for Embedded Systems- P39

Model-Based Design for Embedded Systems- P39: This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. | 346 Model-Based Design for Embedded Systems the core to the iMesh on-chip network. The combination of a core and a switch form the basic building block of the Tilera Processor the tile. Each core is a fully functional processor capable of running complete operating systems and off-the-shelf C code. Each core is optimized to provide a high performance power ratio running at speeds between 600 MHz and 1 GHz with power consumption as low as 170 mW in a typical application. Each core supports standard processor features such as Full access to memory and I O Virtual memory mapping and protection MMU TLB Hierarchical cache with separate L1-I and L1-D Multilevel interrupt support Three-way VLIW pipeline to issue three instructions per cycle The cache subsystem on each tile consists of a high-performance two-level non-blocking cache hierarchy. Each processor tile has a split level 1 cache L1 instruction and L1 data and a level 2 cache keeping the design fast and power efficient. When there is a miss in the level 2 cache of a specific processor the level 2 caches of the other processors are searched for the data before external memory is consulted. This way a large level 3 cache is emulated. This promotes on-chip access and avoids the bottleneck of off-chip global memory. Multicore coherent caching allows a page of shared memory cached on a specific tile to be accessed via load store references to other tiles. Since one tile effectively prefetches for the others this technique can yield significant performance improvements. To fully exploit the available compute power of large numbers of processors a high-bandwidth low-latency interconnect is essential. The network iMesh provides the high-speed data transfer needed to minimize system bottlenecks and to scale applications. iMesh consists of five distinct mesh networks Two networks are completely managed by hardware and are used to move data to and from the tiles and memory in the event of cache misses or DMA transfers. The .

• Phần cứng
• sửa chữa máy tính
• sổ tay phần cứng
• MainBoard
• thiết bị máy tính
• thiết bị mạng
• lắp ráp máy tính
• Phần cứng máy tính
• lỗi máy tính
• hệ thống mạch máy tính
• điện máy tính
• Tài liệu máy tính