TAILIEUCHUNG - Verilog Programming part 18

Timing Controls Various behavioral timing control constructs are available in Verilog. In Verilog, if there are no timing control statements | Timing Controls Various behavioral timing control constructs are available in Verilog. In Verilog if there are no timing control statements the simulation time does not advance. Timing controls provide a way to specify the simulation time at which procedural statements will execute. There are three methods of timing control delay-based timing control event-based timing control and level-sensitive timing control. Delay-Based Timing Control Delay-based timing control in an expression specifies the time duration between when the statement is encountered and when it is executed. We used delay-based timing control statements when writing few modules in the preceding chapters but did not explain them in detail. In this section we will discuss delay-based timing control statements. Delays are specified by the symbol . Syntax for the delaybased timing control statement is shown below. delay3 delay_value delay_value delay_value delay_value delay2 delay_value delay_value delay_value delay_value unsigned_number parameter_identifier specparam_identifier mintypmax_expression Delay-based timing control can be specified by a number identifier or a mintypmax_expression. There are three types of delay control for procedural assignments regular delay control intra-assignment delay control and zero delay control. Regular delay control Regular delay control is used when a non-zero delay is specified to the left of a procedural assignment. Usage of regular delay control is shown in Example 7-10. Example 7-10 Regular Delay Control define parameters parameter latency 20 parameter delta 2 define register variables reg x y z p q initial begin x 0 no delay control 10 y 1 delay control with a number. Delay execution of y 1 by 10 units latency z 0 Delay control with identifier. Delay of 20 units latency delta p 1 Delay control with expression y x x 1 Delay control with identifier. Take value of y. 4 5 6 q 0 Minimum typical and maximum delay values. Discussed in gate-level modeling .

• Kỹ thuật lập trình
• thủ thuật lập trình
• tài liệu lập trình
• kĩ năng lập trình
• mẹo lập trình
• hướng dẫn lập trình
• Verilog Programming
• kỹ thuật lập trình
• kỹ năng lập trình
• bí quyết lập trình
• phương pháp lập trình
• tư liệu lập trình
• kĩ thuật lập trình
• AutoIT