TAILIEUCHUNG - Áp dụng DSP lập trình trong truyền thông di động P17

The Pleiades Architecture Arthur Abnous, Hui Zhang, Marlene Wan, Varghese George, Vandana Prabhu and Jan Rabaey Rapid advances in portable computing and communication devices require implementations that must not only be highly energy efficient, but they must also be flexible enough to support a variety of multimedia services and communication capabilities. The required flexibility dictates the use of programmable processors in implementing the increasingly sophisticated digital signal processing algorithms that are widely used in portable multimedia terminals | The Application of Programmable DSPs in Mobile Communications Edited by Alan Gatherer and Edgar Auslander Copyright 2002 John Wiley Sons Ltd ISBNs 0-471-48643-4 Hardback 0-470-84590-2 Electronic 17 The Pleiades Architecture Arthur Abnous Hui Zhang Marlene Wan Varghese George Vandana Prabhu and Jan Rabaey Rapid advances in portable computing and communication devices require implementations that must not only be highly energy efficient but they must also be flexible enough to support a variety of multimedia services and communication capabilities. The required flexibility dictates the use of programmable processors in implementing the increasingly sophisticated digital signal processing algorithms that are widely used in portable multimedia terminals. However compared to custom application-specific solutions programmable processors often incur significant penalties in energy efficiency and performance. The architectural approach presented in this chapter involves trading off flexibility for increased efficiency. This approach is based on the observation that for a given domain of signal processing algorithms the underlying computational kernels that account for a large fraction of execution time and energy are very similar. By executing the dominant kernels of a given domain of algorithms on dedicated optimized processing elements that can execute those kernels with a minimum of energy overhead significant energy savings can potentially be achieved. Thus this approach yields processors that are domain-specific. In this chapter a reusable architecture template or platform named Pleiades 1 2 that can be used to implement domain-specific programmable processors for digital signal processing algorithms will be presented. The Pleiades architecture relies on a heterogeneous network of processing elements optimized for a given domain of algorithms that can be reconfigured at run time to execute the dominant kernels of the given domain. To verify the effectiveness of the .

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• truyền thông di động
• áp dụng DSP
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• bí quyết lập trình