TAILIEUCHUNG - A novel controllable BIST circuit for embedded SRAM

This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testing operation modes. It controls the test patterns with three additional input ports. | The Open Electrical Electronic Engineering Journal 2016 10 1-10 1 Send Orders for Reprints to reprints@ BENTHAM OPEN CrossMark The Open Electrical Electronic Engineering Journal Content list available at TOEEJ DOI 1874129001610010001 A Novel Controllable BIST Circuit for embedded SRAM Zhiting Lin Chunyu Peng and Kun Wang School of Electronics and Information Engineering Anhui University Peoples Republic of China Abstract With increasingly stringent requirements for memory test the complexity of the test algorithm is increasing. This will make BIST Build-In-Self-Test circuit more complex and the area of BIST circuit larger. This paper proposes a novel controllable BIST circuit. The controllable BIST circuit provides a cost-effective solution that supports a variety of March algorithms and SRAM embedded testing operation modes. It controls the test patterns with three additional input ports. And it indicates the algorithm progress the test result and the number of fails with three output ports. To achieve test patterns generation analy-sis and test results recording the proposed BIST circuit contains five internal functional modules which are Address Gener-ator Control Generator Data Generator Data Comparator and Fail Accumulator. The test patterns of the proposed BIST cir-cuit are controlled by external signals. It is not only suitable for any existing march algorithms but also leaves room for ex-tension if needed. Keywords Controllable BIST Hardware overhead March algorithm SRAM. 1. INTRODUCTION As the size of semiconductor SRAMs becomes larger and larger it s more and more difficult and expensive to test the memories 1 2 . BIST is a widely used method for the detection of manufacturing defects and operational faults in DFT Design for Testability of memory to enhance the yield 3 4 . BIST technology transfers external test to inside by realizing test modules such as the test pattern generator BIST controller and .

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