Đang chuẩn bị nút TẢI XUỐNG, xin hãy chờ
Tải xuống
ECE 551 Digital Design And Synthesis: Lecture 9 has many contents: Internal Synthesizer Flow, Getting Lost in a Sea of Documentation, Optimization in Synthesis, Optimization Phases, Architectural Optimization, Logic/Gate-Level Optimization, Combinational Optimization, Decomposition Example, Register Retiming Example,. | ECE 551 Digital Design And Synthesis Fall ‘09 Synthesis Flow Synthesis Optimizations Administrative Matters Project Demos will be held in B555 Wednesday (12/16/09) from 1:00PM till evening. Friday (12/18/09) from 1:00PM till evening. Final Exam is: Tuesday: 12/22/09 @ 10:05AM Internal Synthesizer Flow Parsing and Syntax & Semantic Error Checking Translation (Elaboration) Synthesizer Policy Checking Architectural Optimization Multi-Level Logic Optimization Technology Mapping Technology-Based Implementation (netlist) Technology Library Structural Representation HDL Description Getting Lost in a Sea of Documentation Add the following line to your .cshrc: alias synopsys_doc ‘acroread /afs/.engr.wisc.edu/apps/eda/synopsys/ syn_Z-2007.03-SP3/doc/online/top.pdf’ Use this to kick off the Synopsys On-Line Documentation (SOLD) Only look at Design Compiler Related Stuff Command Line Interface Guide Constraints and Timing Optimization and Timing Analysis Full command set (on 2nd page) (Synthesis Commands) (man2) Initial Steps (Analyze Verilog File) Parsing for Syntax and Semantics Checking Gives error messages and warnings to user User may modify the HDL description in response Synthesizer Policy Checking Check for adherence to allowable language constructs Check for usage recommendations This is where you find out you can’t use certain Verilog constructs This is synthesizer-dependent Example: Design Vision allows indexed part-select (guess[i*2 : 2]), but the Xilinx Foundation tool does not Certain things common to MOST synthesizers Translation (Elaboration) Builds a structural representation of the design Like a netlist, but includes larger components Not just gate-level, may include adders, etc. Gives additional errors or warnings to the user Issues in initial transformation to hardware. Affects quality achieved by optimization steps Structural representation depends on HDL quality Poor HDL can prevent optimization Optimization in Synthesis None of . | ECE 551 Digital Design And Synthesis Fall ‘09 Synthesis Flow Synthesis Optimizations Administrative Matters Project Demos will be held in B555 Wednesday (12/16/09) from 1:00PM till evening. Friday (12/18/09) from 1:00PM till evening. Final Exam is: Tuesday: 12/22/09 @ 10:05AM Internal Synthesizer Flow Parsing and Syntax & Semantic Error Checking Translation (Elaboration) Synthesizer Policy Checking Architectural Optimization Multi-Level Logic Optimization Technology Mapping Technology-Based Implementation (netlist) Technology Library Structural Representation HDL Description Getting Lost in a Sea of Documentation Add the following line to your .cshrc: alias synopsys_doc ‘acroread /afs/.engr.wisc.edu/apps/eda/synopsys/ syn_Z-2007.03-SP3/doc/online/top.pdf’ Use this to kick off the Synopsys On-Line Documentation (SOLD) Only look at Design Compiler Related Stuff Command Line Interface Guide Constraints and Timing Optimization and Timing Analysis Full command set (on 2nd page)
