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Tham khảo tài liệu 'adaptive techniques for dynamic processor optimization_theory and practice episode 1 part 6', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 88 James Tschanz the core during normal operation. The DAB controller drives the dynamic frequency unit body bias generators and voltage setting of the off-chip VRM to dynamically adapt frequency body bias and VCC to achieve optimum settings for the given conditions. This DAB controller Figure 4.14 is based on a lookup table which is indexed by the output of the thermal droop and current sensors and is loaded with pre-characterized data representing the optimum VCC body bias and frequency for each of the sensor combinations. The control also includes programmable timers and logic to ensure that transitions in VCC body bias and frequency happen in the correct sequence needed for fault-free operation and to eliminate instability around the sensor trip points. The control is designed to be fast enough to respond to 2nd and 3rd droops in voltage as well as changes in temperature and overall chip activity factor. Figure 4.14 Organization of the dynamic adaptive bias controller and the interface to the dynamic clocking and body bias circuits 10 . 2007 IEEE Responding to the relatively fast VCC droops also requires a method for changing frequency quickly without waiting for a PLL to relock. The clocking subsystem shown in Figure 4.15 contains three PLLs running at independent frequencies and a multiplexer to select between them in a single cycle while ensuring that there are no shortened clock cycles. Several algorithms for changing frequency by switching between multiple PLLs are implemented as part of the frequency control including a simple algorithm which switches between three locked PLLs to a flexible algorithm which keeps one PLL always locked at a frequency higher and lower than the current frequency. When a frequency change is requested a Chapter 4 Dynamic Adaptation Using Body Bias Supply Voltage and Frequency 89 switch is made to the slower or faster PLL and then the other two PLLs are relocked and the process repeated. This allows the entire frequency space to
