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Adaptive Techniques for Dynamic Processor Optimization_Theory and Practice Episode 1 Part 2

Tham khảo tài liệu 'adaptive techniques for dynamic processor optimization_theory and practice episode 1 part 2', kỹ thuật - công nghệ, cơ khí - chế tạo máy phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | Figure 1.4 An illustration of critical paths in a design 4 . 2004 IEEE A typical histogram of delay path segments is shown in Figure 1.4 4 . As seen from observing this histogram many of the paths are much faster than the slowest path and this variation represents a further opportunity to reduce power. The transistors in the faster paths can be substituted with transistors with lower leakage. One way to do this is by selective use of transistors with longer channel length. Due to the longer channel length these transistors will be slower but they will also have reduced leakage. An example of this has already been implemented in an integrated circuit 5 through the use of a library of circuits that were implemented with both long and short gate lengths. A slight area penalty was incurred to make each circuit in the library footprint and layout compatible as in Figure 1.5. Hence these circuits can be freely interchanged at any point in the design cycle to minimize power at the expense of path delay. This algorithm can be similarly implemented using multiple threshold voltage transistors. The use of the above algorithm for substitution of longer gate length transistors to reduce leakage can occur on a massive scale as is shown in Figure 1.6. One result of implementing this type of algorithm is that all delay path segments become more critical as the extra slack in the design is harvested in order to reduce leakage current. Making all these paths more critical will tend to make the design less tolerant of circuit variations or circuit modeling inaccuracies. 6 David Scott Alice Wang Nom 10 All transistors can be either nominal or long-Le Most library cells are available in both flavors Long-Le transistors are about 10 slower but have 3x lower leakage All paths with timing slack use long-Le transistors Initial design uses only long channel devices Figure 1.5 Two transistors with the same layout footprint. Layout area efficiency is sacrificed in order to make the shorter .