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Models in Hardware Testing- P5

Models in Hardware Testing- P5:Model based testing is one of the most powerful techniques for testing hardware and software systems.While moving forward to nanoscaled CMOS circuits, we observe a plethora of new defect mechanisms, which require increasing efforts in systematic fault modeling and appropriate algorithms for test generation, fault simulation and diagnosis. | 110 B. Becker and I. Polian one defect resistance O-FC f is set to 100 . As in the case of P-FC to calculate G-FC E-FC and O-FC of a fault list the values for individual faults are averaged. It is obvious that P - FC E - FC G - FC O - FC holds. This means that E-FC and O-FC can be used as lower and upper bounds of the exact fault coverage G-FC for large circuits for which G-FC cannot be computed. The subsequent sections will provide more details on algorithms for resistive fault simulation and ATPG. Fault simulation computes fault coverages with respect to the definitions given above. The main part of a fault simulation procedure is to obtain C-ADI of a fault. ATPG attempts to find a test pattern for a specific defect or prove that this defect is redundant. If done consequently ATPG yields G-ADI as a by-product and allows the calculation of G-FC. 4.2 Interval-Based Fault Simulation Interval-based fault simulation is the simplest algorithm to determine the resistive bridging fault RBF coverage of a test set. It is based on an electrical analysis and construction of analogue detection intervals ADIs at fault site and the propagation of the ADIs to the outputs of the circuit. C-ADI of a fault is obtained by aggregating the ADIs at different outputs for all test patterns in a test set. Fault coverage is then calculated as outlined in the previous section. Figure 4.1 shows the pseudo code of the fault simulation procedure RBF_FSIM. It takes the circuit and the technology parameters needed for electrical analysis at the Procedure RBF_FSIM Input Circuit CKT technology parameters fault listF 2 test set T zh t2 Optional input G for all g F. Output C for all g F P-FC E-FC O-FC G-FC if G-ADIs provided 1 for each g F C fi 0 2 for each t g T begin 3 for each g F begin 4 perform good-simulation 5 determine critical resistances Ri Fm at fault site 6 construct local ADIs 0 F 7 propagate ADIs to circuit output 8 for each circuit output with ADI A 9 CK Cft uA 10 end for 11 end for .