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Ôxi hoá - trong quá trình chế tạo mạch tích hợp người ta thường phải dùng lớp SiO2 trên bề mặt tinh thể Si Lớp SiO2 này có hệ số dãn nở nhiệt gần bằng hệ số giản nở nhiệt của Si, với hằng số điện môi ~ 4, có tác dụng bảo vệ bề mặt các linh kiện bán dẫn dưới tác dụng của môi trường bên ngoài, che chắn bề mặt Si trong quá trình khuếch tán định xứ các tạp chất như P và B. | At this stage the drain and source diffusions for both the n-channel and p-channel transistors arc added. Although two different types of diffusions and hence two separate masks are required the designer need specify only one of the two masks in this process only those areas not protected by field oxide arc capable of accepting any diffusion impurities. This is termed the moat or active region. It is further provided in this process that any moat area that is not exposed to n-type impurities will be exposed to p-type impurities. Consequently the designer selects those moat regions that are to become p-type with Mask 4 which is termed the p select mask. The n select mask Mask 5 which is used to pattern those regions of moat that are to become n-typc is automatically generated from the complement of the p select mask intersected with the moat active mask. p select is used in the substrate to form p-channel transistors and interconnects and is used in the p-wcll to provide ohmic contact to the p-well as well as for guard rings. Correspondingly n select is used in the p-well to form n-channel transistors and interconnects and in the substrate to make top ohmic contacts as well as additional guard rings. Further comments about guard rings and their role in latch-up protection appear in Section 2.4. As was the case in the NMOS process the polysilicon layer or layers are patterned prior to the p and n diffusions. The poly silicon that lies in the moat serves as a diffusion mask for these diffusions and provides self-alignment of the gate with the drain and source regions The n and diffusions are much shallower than the p-well diffusion and arc typically in the 5000 Ả and 7000 Ả ranges respectively. Following the p and n diffusions which occur prior to Step 36 in the process scenario the cross-sectional profile is as shown in Fig. 2B.1Ổ. The n-channel and p-channel transistors along with the ohmic contacts and guard rings arc clearly visible at this stage. A thick .
