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Cryptographic Algorithms on Reconfigurable Hardware- P11: This chapter presents a complete outhne for this Book. It explains the main goals pursued, the strategies chosen to achieve those goals, and a summary of the material to be covered throughout this Book. | 9.5 AES Implementations on FPGAs 279 Fig. 9.26. S-Box and Inv S-Box Using a Different MI b Same MI transformation AF . For decryption inverse affine transformation IAF is applied first followed by MI step. Implementing MI as look-up table requires memory modules therefore a separated implementation of BS IBS causes the allocation of high memory requirements especially for a fully pipelined architecture. We can reduce such requirements by developing a single data path which uses one MI block for encryption and decryption. Figure 9.26 shows the BS IBS implementation using single block for MI. There are two design approaches for implementing MI look-up table method and composite field calculation. MI Using Look-Up Table Method MI can be implemented using memory modules BRAMs of FPGAs by storing pre-computed values of MI. By configuring a dual port BRAM into two single port BRAMs 8 BRAMs are required for one stage of a pipeline architecture hence a total of 80 BRAMs are used for 10 stages. A separated implementation of AF and IAF is made. Data path selection for encryption and decryption is performed by using two multiplexers which are switched depending on the E D signal. A complete description of this approach is shown in Figure 9.27 The data path for both encryption and decryption is therefore as follows Encryption MI AF SR MC ARK Decryption ISR IAF MI IMC IARK The design targets Xilinx VirtexE FPGA devices XCV2600 and occupies 80 BRAMs 43 386 I O blocks 48 and 5677 CLB slices 22.3 . It runs at 30 MHz and data is processed at 3840 Mbits s. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. 280 9. Architectural Designs For the Advanced Encryption Standard Fig. 9.27. Data Path for Encryption Decryption The data blocks are accepted at each clock cycle and then after 11 cycles output encrypted decrypted blocks appear at the output at consecutive clock cycles. It is an efficient fully pipeline encryptor decryptor core for those cryptographic .
