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Chapter 9 - TRAP routines. This chapter presents the following content: Privileged instructions, TRAP routines, subroutines, the complete mechanism, TRAP routines for handling I/O, TRAP routine for halting the computer, saving and restoring registers, the call/return mechanism, | Chapter 9 TRAP Routines Privileged Instructions TRAP Routines Subroutines Privileged Instructions There are several instructions that are best executed by a supervisor program (OS) rather than a user program: IO instructions Loading of memory-mapped registers Resetting the clock Halt i.e. instructions where one program can affect the behavior of another. The CPU can be designed to enforce two modes of operation: User Mode Privileged Mode (aka. supervisor, kernel, monitor mode) Only the supervisor program (OS) can execute privileged instructions. 9 - TRAP Instructions TRAPs insulate critical tasks from the user with or without privilege enforcement The TRAP mechanism: A set of trap service routines or TSRs (part of the CPU OS) We have already seen the basic I/O SRs A table of the starting addresses of these service routines Located in a pre-defined block of memory called the Trap Vector Table or System Control Block In the LC-3: from x0000 to x00FF (only 5 currently in use) The TRAP instruction which loads the starting address of the TSR into the PC Return link from the end of the TSR back to the original program. 9 - LC-3 TRAP Routines GETC (TRAP x20) Read a single character from KBD. Write ASCII code to R0[7:0], clear R0[15:8]. OUT (TRAP x21) Write R0[7:0] to the monitor. PUTS (TRAP x22) Write a string to monitor (address of first character of string is in R0). IN (TRAP x23) Print a prompt to the monitor and read a single character from KBD. Write ASCII code to R0[7:0], clear R0[15:8], echo character to the monitor. HALT (TRAP x25) Print message to monitor & halt execution. Trap vector table 9 - TRAP Instructions TRAP: A special instruction A form of subroutine call used to invoke a service routine. If privilege is being enforced, it switches the execution to privileged mode, and reverts back to user mode when the TSR completes. R7 (PC) ; the current PC is stored in R7 PC Mem[ Zext( IR[7:0] ) ] ; the 8-bit trap vector is loaded to the PC RET – | Chapter 9 TRAP Routines Privileged Instructions TRAP Routines Subroutines Privileged Instructions There are several instructions that are best executed by a supervisor program (OS) rather than a user program: IO instructions Loading of memory-mapped registers Resetting the clock Halt i.e. instructions where one program can affect the behavior of another. The CPU can be designed to enforce two modes of operation: User Mode Privileged Mode (aka. supervisor, kernel, monitor mode) Only the supervisor program (OS) can execute privileged instructions. 9 - TRAP Instructions TRAPs insulate critical tasks from the user with or without privilege enforcement The TRAP mechanism: A set of trap service routines or TSRs (part of the CPU OS) We have already seen the basic I/O SRs A table of the starting addresses of these service routines Located in a pre-defined block of memory called the Trap Vector Table or System Control Block In the LC-3: from x0000 to x00FF (only 5 currently in use) The
