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Handbook of Algorithms for Physical Design Automation part 68 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 652 Handbook of Algorithms for Physical Design Automation block width. The graph GV is constructed similarly. The respective width Wc and height Hc of the chip can be computed by applying a longest-path algorithm on GH and GV. Then the algorithm divides the dead spaces and routing channels into tiles to facilitate buffer block planning. For each tile its area slack is computed from the longest paths in GH and GV. For dead spaces and routing channels that are not on the critical paths of the constraint graph GH GV they will each have a positive area slack in width height . If there are buffers required to be inserted to meet timing constraints the algorithm picks a tile that can accommodate the most number of these buffers and then inserts appropriate buffers into this tile. If there are no tiles with positive area slack we have to shift some circuit blocks for the buffer insertion thereby increasing the overall chip area. This block shifting might make rooms for other tiles resulting in new positive slacks for these tiles. We pick the dead space or the routing channel with the maximum buffer-insertion demand and then select one tile in it. For the selected tile we insert appropriate buffers into the tile. If there is not sufficient space in the tile for buffer insertion the associated routing channel will be expanded to make room for the buffers. After inserting buffers into the selected tile the information of the constraint graphs feasible regions and the chip dimension is updated and the buffer insertion clustering process is repeated until all buffers are placed. More recently there have been attempts to perform simultaneous buffer block planning and floorplanning to fully utilize useful dead spaces for performance optimization 10-13 . Jiang et al. provided a generic paradigm along this direction in Ref. 11 . The algorithm presented in Ref. 11 simultaneously considers floorplanning and buffer blockplanning for a general floorplan. The method adopts simulated .
