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Handbook of Algorithms for Physical Design Automation part 98 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 952 Handbook of Algorithms for Physical Design Automation FIGURE 45.15 Memory logic interconnect block. interconnect blocks crosses indicate programmable connections. The flexibility of the connection block Fm can be defined as the number of programmable connections available between each horizontal pin and the adjacent vertical channel. In Figure 45.14 Fm 4. In Ref. Wilton99 it is shown that a value of Fm between 4 and 7 works well. To increase routability the architecture in Figure 45.14 includes dedicated tracks for memory-to-memory connections. These tracks are used when multiple memory arrays are cascaded together to form larger user arrays and are more efficient for such memory-to-memoryconnections. EMBs can also be used to implement logic by configuring them as large ROMs Cong98 WiltonOO . 45.5.2 Distributed Memory Commercial FPGAs such as Xilinx s Virtex-4 Virtex-II and Spartan-3 devices allow the 4-input LUTs in their logic blocks to be configured as 16 x 1-bit memories Xilinx05a . These memories have synchronous inputs. Their outputs can be synchronous through the use of the LUTs associated register. These 16 x 1-bit memories can also be cascaded to implement deeper or wider memory arrays through specialized logic resources. Another method for supporting distributed memory is proposed in Ref. Oldridge05 . This architecture allows the configuration memory in the interconnect switch blocks to be used as user memory and is very efficient for wide shallow memories. 45.6 EMBEDDED COMPUTATION BLOCKS 45.6.1 Multipliers and DSP Blocks To address the performance requirements of digital signal processing DSP applications FPGA manufacturers typically include dedicated hardware multipliers in their devices. Altera Cyclone II and Xilinx Virtex-II -II Pro devices include embedded 18x18-bit multipliers which can be split into 9x9-bit multipliers Xilinx05a . The Virtex-II -II Pro devices are further optimized with direct connections to the Xilinx block RAM resources for
