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Handbook of Algorithms for Physical Design Automation part 29 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 262 Handbook of Algorithms for Physical Design Automation but again the routing is done flat. In the same spirit many floorplanners support operations such as edit in context to enable the user to treat a hierarchical design as flat where this is beneficial without actually flattening the design. 13.3.1 Is Hierarchical Design Less Efficient It is sometimes argued that a hierarchical design is intrinsically less efficient than a flat design in terms of area or performance. While this has some basis in practice it is not true in theory if arbitrary rearrangement of the hierarchy is allowed. This can be shown as follows 28 take the result of the hypothetically more efficient flat tool or procedure. Then divide this flat design cookie cutter style to create a hierarchical design. This design if fabricated would be exactly the same as the flat design and have exactly the same size and performance. This exact procedure is only useful as an existence proof because there is no point in building a hierarchical design that is exactly the same as an existing flat design. Furthermore the cookie cutter approach will almost surely result in a completely incomprehensible hierarchy. There may be no easy way to express high-level constraints on the block pins indeed even the pins may be split into subpieces. But this procedure does show that the problem is the limitations of hierarchical tools not the use of hierarchy itself. A very similar procedure has been used to limit the scope of changes during ECOs 29 . This showed empirically that this procedure not only generate hierarchical designs with the same efficiency as the corresponding flat designs but also that under normal conditions no huge cells this can be done even when restricted to slicing floorplans. 13.3.2 Logical versus Physical Hierarchy Normally the input to an industrial floorplanner is a netlist defined in structural Verilog or VHDL. Usually any hierarchy present in the original Verilog or VHDL files was developed .
