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Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article APRON: A Cellular Processor Array Simulation and Hardware Design Tool | Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2009 Article ID 751687 9 pages doi 10.1155 2009 751687 Research Article APRON A Cellular Processor Array Simulation and Hardware Design Tool David R. W. Barr and Piotr Dudek School of Electrical and Electronic Engineering The University of Manchester P. O. Box 88 Manchester M60 1QD UK Correspondence should be addressed to David R. W. Barr d.barr@postgrad.manchester.ac.uk Received 12 September 2008 Accepted 21 March 2009 Recommended by David Lopez Vilarino We present a software environment for the efficient simulation of cellular processor arrays CPAs . This software APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays topographic multilayer neural networks vision chips with SIMD processor arrays and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems allowing more users to develop algorithms for CPA systems. Copyright 2009 D. R. W. Barr and P. Dudek. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. 1. Introduction Massively parallel processing systems have been the topic of high-performance computing research and design for many years 1-4 but in recent years single-chip implementations of such systems are becoming a reality. Cellular processor arrays CPAs such as the ones presented in 510 .
