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Architecture and Instruction Set of the C6x Processor • • • • • Architecture and instruction set of the TMS320C6x processor Addressing modes Assembler directives Linear assembler Programming examples using C, assembly, and linear assembly code 3.1 INTRODUCTION Texas Instruments introduced the first-generation TMS32010 digital signal processor in 1982, the TMS320C25 in 1986 [1], and the TMS320C50 in 1991. Several versions of each of these processors—C1x, C2x, and C5x—are available with different features, such as faster execution speed. These 16-bit processors are all fixed-point processors and are code-compatible. In a von Neumann architecture, program instructions and data are stored in a single memory. | DSP Applications Using C and the TMS320C6x DSK. Rulph Chassaing Copyright 2002 John Wiley Sons Inc. ISBNs 0-471-20754-3 Hardback 0-471-22112-0 Electronic 3 Architecture and Instruction Set of the C6x Processor Architecture and instruction set of the TMS320C6x processor Addressing modes Assembler directives Linear assembler Programming examples using C assembly and linear assembly code 3.1 INTRODUCTION Texas Instruments introduced the first-generation TMS32010 digital signal processor in 1982 the TMS320C25 in 1986 1 and the TMS320C50 in 1991. Several versions of each of these processors C1x C2x and C5x are available with different features such as faster execution speed. These 16-bit processors are all fixed-point processors and are code-compatible. In a von Neumann architecture program instructions and data are stored in a single memory space. A processor with a von Neumann architecture can make a read or a write to memory during each instruction cycle. Typical DSP applications require several accesses to memory within one instruction cycle. The fixed-point processors C1x C2x and C5x are based on a modified Harvard architecture with separate memory spaces for data and instructions that allow concurrent accesses. Quantization error or round-off noise from an ADC is a concern with a fixed-point processor. An ADC uses only a best-estimate digital value to represent an input. For example consider an ADC with a word length of 8 bits and an input range of 1.5 V. The steps represented by the ADC are input range 28 3 256 11.72mV. This produces errors which can be up to 11.72mV 2 5.86mV. Only a best estimate can be used by the ADC to represent input values that are not multiples of 61 62 Architecture and Instruction Set of the C6x Processor 11.72 mV. With an 8-bit ADC 28 or 256 different levels can represent the input signal. An ADC with a larger word length such as a 16-bit ADC currently very common can reduce the quantization error yielding a higher resolution. The more .
