Đang chuẩn bị nút TẢI XUỐNG, xin hãy chờ
Tải xuống
và đẳng thời. Đối với máy tính truyền thống bộ nhớ ánh xạ, tải, và các ứng dụng lưu trữ, chuyển giao không đồng bộ là thích hợp và đầy đủ. Chuyển giao dữ liệu đẳng thời cung cấp cho vận chuyển dữ liệu được đảm bảo ở một tỷ lệ được xác định trước. | 2.3 CENTRAL PROCESSING UNIT 29 can support the multiple speeds on a single bus and is flexible - the standard supports freeform daisy chaining and branching for peer-to-peer implementations. It is also hot pluggable that is devices can be added and removed while the bus is active. FireWire supports two types of data transfer asynchronous and isochronous. For traditional computer memory-mapped load and store applications asynchronous transfer is appropriate and adequate. Isochronous data transfer provides guaranteed data transport at a predetermined rate. This is especially important for multimedia applications where uninterrupted transport of time-critical data and just-in-time delivery reduce the need for costly buffering. This makes it ideal for devices that need to transfer high levels of data in real time such as cameras VCRs and televisions. 2.3 CENTRAL PROCESSING UNIT A reasonable understanding of the internal organization of the CPU is quite helpful in understanding the basic principles of real-time response hence those concepts are briefly reviewed here.1 The CPU can be thought of as containing several components connected by its own internal bus which is distinct from the memory and address buses of the system. As shown in Figure 2.6 the CPU contains a program counter PC an arithmetic logic unit ALU internal CPU memory-scratch pad memory and CPU Figure 2.6 Partial stylized internal structure of a typical CPU. The internal paths represent connections to the internal bus structure. The connection to the system bus is shown on the right. 1 Some of the following discussion in this section is adapted from Computer Architecture A Minimalist Perspective by Gilreath and Laplante Gilreath03 . 30 2 HARDWARE CONSIDERATIONS micromemory general registers labelled R1 through Rn an instruction register IR and a control unit CU . In addition a memory address register MAR holds the address of the memory location to be acted on and a memory date register MDR holds the data
