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A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examples such as Crusoe and DAISY, however, have used existing hardware instruction sets as virtual ISAs, which complicates translation and optimization. In fact, there has been little research on specific designs for a virtual ISA for processors. This paper proposes a novel virtual ISA (LLVA) and a translation strategy for implementing it on arbitrary hardware. The instruction set is typed, uses an infinite virtual register set in Static Single Assignment form, and provides explicit control-flow and dataflow information, and. | 5 THE INSTRUCTION SET ARCHITECTURE LEVEL 1 Figure 5-1. The ISA level is the interface between the compilers and the hardware. Address 8 Bytes------------ - 24 16 15 i 14 i 13 12 i 11 i 10 i 9 8 8 0 Address 8 Bytes------------ - 24 19 18 17 16 16 15 14 13 12 8 L 0 Aligned 8-byte word at address 8 Nonaligned 8-byte word at address 12 a b Figure 5-2. An 8-byte word in a little-endian memory. a Aligned. b Not aligned. Some machines require that words in memory be .
