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Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Editorial FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2009 Article ID218456 2 pages doi 10.1155 2009 218456 Editorial FPGA Supercomputing Platforms Architectures and Techniques for Accelerating Computationally Complex Algorithms Vinay Sriram1 and Miriam Leeser2 1 Defence and Systems Institute University of South Australia Adelaide South Australia 5001 Australia 2 Department of Electrical and Computer Engineering College of Engineering Northeastern University Boston MA 02115 USA Correspondence should be addressed to Miriam Leeser mel@coe.neu.edu Received 6 May 2009 Accepted 6 May 2009 Copyright 2009 V. Sriram and M. Leeser. This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited. This is a special issue on FPGA supercomputing platforms architectures and techniques for accelerating computationally complex algorithms. This issue covers a broad range of applications in which field programmable gate arrays FPGAs are successfully used to accelerate processing. It also provides researcher s insights on the challenges in successfully using FPGAs. The applications discussed include motor control radar processing face recognition processing seismic data and accelerating random number generation. Techniques discussed by the authors include partitioning between a CPU and FPGA hardware reducing bitwidth to improve performance interfacing to analog signals and using high level tools to develop applications. Two challenges that face many users of reconfigurable hardware are interfacing to the analog domain and easing the job of developing applications. In the paper entitled Prototyping Advanced Control Systems on FPGA the authors present a rapid prototyping platform and design flow suitable for the design of onchip motion controllers and other SoCs with a need for analog interfacing. The target hardware .
