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Introduction to Programmable Logic Architectures Trong một số chương trong quá khứ, chúng tôi đã được sử dụng Alteraâ € ™ sMAX PLUS II phần mềm để làm cho mạch thiết kế để tải về vào một thiết bị logic lập trình phức tạp (CPLD). đối xử với thiết bị này như một cái gì đó boxâ € "đen có chức năng chúng tôi thiết kế, nhưng có cấu trúc chúng ta không thực sự hiểu. Trong chương này, chúng tôi sẽ nhìn vào bên trong hộp | CHAPTER ll ll ll ll fviiiiiiiiiii illlllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll Introduction to Programmable Logic Architectures OUTLINE CHAPTER OBJECTIVES 8.1 Programmable Sum-of-Products Arrays 8.2 PAL Fuse Matrix and Combinational Outputs 8.3 PAL Outputs with Programmable Polarity 8.4 PAL Devices with Programmable Polarity 8.5 Universal PAL and Generic Array Logic 8.6 MAX7000S CPLD 8.7 FLEX10K CPLD Upon successful completion of this chapter you will be able to Draw a diagram showing the basic hardware conventions for a sum-of-products-type programmable logic device. Describe the structure of a programmable array logic PAL AND matrix. Draw fuses on the logic diagram of a PAL to implement simple logic functions. Describe the structures of combinational programmable polarity and registered PAL outputs. Determine the number and type of outputs from a PAL GAL part number. Explain the structure of an output logic macrocell OLMC . State differences between Universal PAL and generic array logic GAL and standard PAL. Interpret the logic diagrams of Universal PAL and GAL devices to determine the number of outputs and product terms and the type of control signals available in a device. Interpret block diagrams to determine the basic structure of an Altera MAX7000S CPLD including macrocell configuration Logic Array Blocks LABs control signals and product term expanders. State the differences between PLDs based on sum-of-products SOP architecture versus look-up table LUT architecture. Interpret block diagrams to determine the basic structure of a logic element in an Altera FLEX10K CPLD including look-up tables cascade chains carry chains and control signals. Interpret block diagrams to determine how a logic element in a FLEX10K device relates to the overall structure of the device. Interpret block diagrams to determine how logic
