Đang chuẩn bị nút TẢI XUỐNG, xin hãy chờ
Tải xuống
High Level Synthesis: from Algorithm to Digital Circuit- P31: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia. "High-Level Synthesis: from Algorithm to Digital Circuit" should be on each designer's and CAD developer's shelf, as well as on those of project managers who will soon embrace high level design and synthesis for all aspects of digital system design. | 15 High-Level Synthesis Algorithms for Power and Temperature Minimization 291 thermal effects must be considered during leakage power optimization. We will later survey thermal-aware leakage optimization techniques. 15.2.3 Importance of Incorporating Physical Design Within High-Level Synthesis It is becoming increasingly important to consider physical design decisions within high-level synthesis. Interconnect power consumption and delay are increasing relative to logic delay. Increasing power densities are making it necessary to determine and optimize the IC thermal profile at design time computing a thermal profile requires a power profile. Determining the interconnect structure and power profile depends on the knowledge of the IC floorplan. As a result a number of researchers have considered the impact of physical details e.g. floorplanning information on high-level synthesis 40-46 . Taking interconnect power consumption and delay into consideration during high-level synthesis has attracted significant attention. In previous work 47-51 the number of interconnects or multiplexers was used to estimate the interconnect cost. The performance and power impact of the interconnect and interconnect buffers are now first-order considerations 52 . It is no longer possible to accurately predict the power consumption and performance of a design without first knowing enough about its floorplan to predict the structure of its interconnect. This change has complicated both design and synthesis. For this reason a number of researchers have worked on interconnect-aware high-level synthesis algorithms 53-55 . These approaches typically use a loosely coupled independent floorplanner for physical estimation. This technique has the advantage of allowing estimation of physical properties but has a drawback. Creating a floorplan from scratch for each high-level synthesis move is inefficient given the fact that the new floorplan frequently has only small differences with the previous .
