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Serial Port RS 232 UART Programming | 8250 14450 16550 UART INTERNAL ARCHITECTURE There are 10 Internal Regs 1 Rx Buffer Reg Rx reg. OFFSET 0 DLAB 0 Tx Buffer Reg Holding Reg Tx Reg. 2 Interrupt Enable Reg R W OFFSET 1 D0 RDA D1 TBE D2 Rx error or Break. Framing Overrun and parity error. D3 RS 232 Input. Interrupt occurs when any RS 232 input changes state. D4-d7 0000 1 2 Interrupt Identification OFFSET 2 R only Used to identify the exact source of interrupt. D3 indicates that pending Tx or Rx interrupt was generated by timeout. D3 D2 D1 DO Priority Interrupt ID 0001 None None 0110 0 HI Highest priority. serialization error framing parity overrun or Break 0100 1 RDA FIFO Rx Trigger level reached like RDA for FIFO 1100 1 FIFO Timeout. No char removed from or input to Rx FIFO during last character times there is at least 1 char during this time. 0010 2 TBE 0000 3 LO RS 232 Input CTS DSR RI DCD 2 4 FIFO Control Register OFFSET 2 W only D0 FIFO Enable. Enables operation of both FIFOs. A zero clears all bytes in FIFOs. D1 Rx FIFO Reset. Clears all bytes from Rx FIFO but NOT the Rx shift reg. D2 Tx FIFO Reset. Clears all bytes from Tx FIFO but NOT the Tx shift reg. D3 DMA Mode Select. Supports DMA Operations D4 D5 Reserved D7 D6 Receive Trigger Level. 00 level 1 01 level 4 10 level 8 11 level 16 5 Line Control Register OFFSET 3 R W Used to specify SDU Serial Data Unit Format D1 D0 OF DATA BITS 00 5 01 6 10 7 11 8 D2 OF STOP BITS. 0 1 Stop bit 1 2 stop bits. 1 U stop bits are automatically selected if 5 data bits are used. D5 D5 D3 PARITY 000 NO Parity 001 Odd 011 Even 101 Mark. Parity fixed to 1 independent of data 111 Space. Parity fixed to 0 independent of data Note What errors can mark and space parity detect D6 BREAK. 0 Break OFF 1 Break ON. A 1 on this bit forces Tx i.e. SOUT pin to a logic 0 state. The Transmitter remains in this state until a 0 is written to this bit. What is the use of this
