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Tham khảo tài liệu 'program c ansi programming embedded systems in c and c++ phần 10', công nghệ thông tin, kỹ thuật lập trình phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | A piece of software that is independent of the processor on which it will be run. Most programs that can be written in a high-level language are processor-independent. Contrast with processor-specific. processor-specific A piece of software that is highly dependent on the processor on which it will be run. Such code must usually be written in assembly language. Contrast with processor-independent. profiler A software development tool that collects and reports execution statistics for your programs. These statistics include the number of calls to each subroutine and the total amount of time spent within each. This data can be used to learn which subroutines are the most critical and therefore demand the greatest code efficiency. program counter See instruction pointer. R RAM Random-Access Memory. A broad classification of memory devices that includes all devices in which individual memory locations can be read or written as required. RISC Reduced Instruction Set Computer. Describes the architecture of a processor family. RISC processors generally feature fixed-length instructions a load-store memory architecture and a large number of general-purpose registers or register windows. The MIPS processor family is an excellent example. Contrast with CISC. ROM Read-Only Memory. A broad classification of memory devices that includes all devices in which the individual memory locations can be read but not written. ROM emulator A debugging tool that takes the place of-or emulates-the ROM on your target board. A ROM emulator acts very much like a debug monitor except that it includes its own serial or network connection to the host. ROM monitor See debug monitor. RTOS Real-Time Operating System. An operating system designed specifically for use in real-time systems. race condition A situation in which the outcome of a program can be affected by the exact order in which the instructions are executed. Race conditions are only an issue where interrupts and or preemption are .
