Đang chuẩn bị nút TẢI XUỐNG, xin hãy chờ
Tải xuống
Model-Based Design for Embedded Systems- P14:The unparalleled flexibility of computation has been a key driver and feature bonanza in the development of a wide range of products across a broad and diverse spectrum of applications such as in the automotive aerospace, health care, consumer electronics, etc. | 366 Model-Based Design for Embedded Systems FIGURE 12.7 Reconfigurable socket abstraction based on the PLBv46 PLBv46 bridge architecture. The PLBv46 slave and PLBv46 master burst blocks are standard IP components and all blocks except the DCR slave block are part of the bridge. Bus macros are implicitly present on all signals crossing the boundary of the reconfigured region. An alternative is to architect the interface around a bus bridge with independent busses in the static region and in the reconfigurable region. The design of the socket is based on partitioning the Xilinx PLBv46 PLBv46 bridge IP 23 as shown in the block diagram in Figure 12.7. Internally this core is based around 32-bit fixed-width data FIFOs and a small number of control signals. Most of the bridge is treated as part of the static region with only a small amount of logic required in the reconfigurable region to complete the bridge. In addition to the bus interface which is primarily used to interface to the reconfigured region the socket core also contains a control interface based on the DCR protocol 7 which is used to generate an independent reset signal to the reconfigurable region and to force signals driven by the reconfigurable module to stable values during reconfiguration. 12.5.3 Direct Memory Access Interfaces The bus interface above is a generic and flexible interface which can be used to communicate with the reconfigured portion of the system in different ways. For instance it may be used by the processor to both send and receive data from the reconfigured region or as a control interface to set parameter values of IP cores executing in the reconfigured region. However it does have several disadvantages. Primarily the bandwidth of data to or from the FPGA Platforms for Embedded Systems 367 processor is limited because of the overhead of bus arbitration and the fact that the memory range is treated as uncached I O transactions. Although performance could be improved somewhat for .
