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DRAM Cell ObservationDRAM Cell Observations.1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.DRAM memory cells are single ended in contrast to SRAM cells.The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. | Digital Integrated Circuits A Design Perspective Semiconductor Memories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO Memory Timing: Definitions Memory Architecture: Decoders Word 0 Word 1 Word 2 Word N 2 2 Word N 2 1 Storage cell M bits M bits N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 Word N 2 2 Word N 2 1 Storage cell S 0 Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output ( M bits) Decoder Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Block Diagram of 4 Mbit SRAM Subglobal row decoder Global row decoder Subglobal row decoder Block 30 Block 31 128 K Array Block 0 Block 1 Clock generator CS, WE buffer I/O buffer Y -address buffer X -address buffer x1/x4 controller Z -address buffer X -address buffer Predecoder and block selector Bit line load Transfer gate Column decoder Sense amplifier and write driver Local row decoder [Hirose90] Contents-Addressable Memory Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 VDD WL BL GND Diode ROM MOS ROM 1 MOS ROM 2 MOS OR ROM WL [0] V DD BL | Digital Integrated Circuits A Design Perspective Semiconductor Memories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO Memory Timing: Definitions Memory Architecture: Decoders Word 0 Word 1 Word 2 Word N 2 2 Word N 2 1 Storage cell M bits M bits N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 Word N 2 2 Word N 2 1 Storage cell S 0 Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output ( M bits) Decoder Array-Structured Memory Architecture Problem: ASPECT RATIO or
