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ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE- P3

ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE- P3: Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. | Statements for Behavioral Descriptions else V out 0.0 for the variable x as some arbitrary function of time is discontinuous at the output about the condition x 2.5 for V out in both time and value. This may or may not be a problem depending upon the type of network to which the output signal V out is attached. For resistive loads these types of discontinuities do not present problems. However for capacitive or inductive loads this type of behavior will potentially cause problems for the simulation. The Verilog-A language provides capabilities for the model developer to effectively handle such cases but still relies on the developer for recognizing and utilizing these capabilities. The mathematical validity and stability of the formulation of a model are important issues to consider when developing a behavioral model particularly during the test and validation of the model. 3.3 Statements for Behavioral Descriptions In the Verilog-A language all analog behavior descriptions are encapsulated within the analog statement. The analog statement encompasses the contribution state-ment s that are used to define the relationships between the input and output signals of the module. Statements within the Verilog-A language allows these contribution statements used in defining the analog behaviors to be sensitive to procedural and or timing control. This section describes the statements used in formulating analog behavioral descriptions. 3.3.1 Analog Statement The analog statement is used for defining the behavior of the model in terms of contribution statements control-flow and or analog event statements. All the state-ment s comprising the analog statement are evaluated at each point during an analysis. The analog statement is the keyword analog followed by a valid Ver-ilog-A statement. Behavioral Descriptions 45 Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark Behavioral Descriptions analog statement Where statement is a single statement in the .