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[ Team LiB ] A.1 Strength Levels Verilog allows signals to have logic values and strength values. Logic values are 0, 1, x, and z. Logic strength values are used to resolve combinations of multiple signals and to represent behavior of actual hardware elements | Team LiB A.1 Strength Levels Verilog allows signals to have logic values and strength values. Logic values are 0 1 x and z. Logic strength values are used to resolve combinations of multiple signals and to represent behavior of actual hardware elements as accurately as possible. Several logic strengths are available. Table A-1 shows the strength levels for signals. Driving strengths are used for signal values that are driven on a net. Storage strengths are used to model charge storage in trireg type nets which are discussed later in this appendix. Table A-1. Strength Levels Strength Level Abbreviation Degree Strength Type supply1 Su1 strongest l driving strong1 St1 driving pull1 Pul driving large1 La1 storage weakl Wel driving medium1 Mel storage small1 Sm1 storage highz1 HiZl weakestl high impedance highz HiZ0 weakest0 high impedance small0 Sm0 storage medium0 Me0 storage weak0 We0 driving large0 La0 storage pull0 Pu0 driving strong0 St0 driving supply0 Su0 strongest0 driving Team LiB Team LiB A.2 Signal Contention Logic strength values can be used to resolve signal contention on nets that have multiple drivers.There are many rules applicable to resolution of contention. However two cases of interest that are most commonly used are described below. A.2.1 Multiple Signals with Same Value and Different Strength If two signals with same known value and different strength drive the same net the signal with the higher strength wins. In the example shown supply strength is greater than pull. Hence Sul wins. A.2.2 Multiple Signals with Opposite Value and Same Strength When two signals with opposite value and same strength combine the resulting value is x. Team LiB Team LiB A.3 Advanced Net Types We discussed resolution of signal contention by using strength levels. There are other methods to resolve contention without using strength levels. Verilog provides advanced net declarations to model logic contention. A.3.1 tri The keywords wire and tri have identical syntax and
