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Mainboard ESC Model C51PVGM | 5 4 3 2 I D C B C51PVGM-M REV 1.1 PCB 15-K57-011100 BOM 89-386-K57122 M2-1 M2-1 M2-3 M2-4 HyperTransport DDR2 Miscellany Power and Ground Page Index 01-COVER PAGE 02-BLOCK DIAGRAM 03-CPU 04-CPU 05-CPU 06-CPU 07-First Logic DDR2 DIMM 08-DDR2 Termination 09-C51PVG 10- C51PVG 11- C51PVG 12- C51PVG 13- C51PVG 14- MCP51G 15- MCP51G 16- MCP51G 17- MCP51G 18- MCP51G 19- MCP51G 20- PCI-E 16 21- PCI 1 2 22- PCI-E 1 CNR 23- LPC 24- LPT 25- USB 26- PWR 27- CPU HT CPU HT MCP51G PCI-E DAC VGA CONN P G HT C51PVG PCI SATA IDE CONN AUDIO USB MISC GMII P G SIO-ITE8716F FDD COM PS2 CONN. FNT PNL VCORE D C B Signature Date 28- DC-DC 29- ALC888 30- ALC888 CONN. 31- RTL8100C 32- 1394 VT6308 A Designer Layout Check Approval Eli Yang Cherry Huntion Tommy 04 10 2006 A Title Size B Elitegroup Computer Systems COVER PAGE Document Number Sheet 1 of 32 1 . Date Thursday October 05 2006 Rev 1.1 D C B A 8 7 6 VLDT_B 51 51 L0_CLKIN_H1 N6 L0_CLKIN_L1 P6 L0_CLKIN_H0 N3 L0_CLKIN_L0 N2 1 L0_CTLIN_H1 V4 1 L0_CTLIN_L1 V5 L0_CTLIN_H0 U1 L0_CTLIN_L0 V1 L0_CADIN_H15 U6 L0_CADIN_L15 V6 L0_CADIN_H14 T4 L0_CADIN_L14 T5 L0_CADIN_H13 R6 L0_CADIN_L13 T6 L0_CADIN_H12 P4 L0_CADIN_L12 P5 L0_CADIN_H11 M4 L0_CADIN_L11 M5 L0_CADIN_H10 L6 L0_CADIN_L10 M6 L0_CADIN_H9 K4 L0_CADIN_L9 K5 L0_CADIN_H8 .16 L0_CADIN_L8 K6 L0_CADIN_H7 113 L0_CADIN_L7 112 L0_CADIN_H6 R1 L0_CADIN_L6 T1 L0_CADIN_H5 R3 L0_CADIN_L5 R2 L0_CADIN_H4 N1 L0_CADIN_L4 P1 L0_CADIN_H3 L1 L0_CADIN_L3 M1 L0_CADIN_H2 L3 L0_CADIN_L2 L2 L0_CADIN_H1 .1 L0_CADIN_L1 K1 L0_CADIN_H0 .3 L0_CADIN_L0 .2 L0_CLKIN_H 1 L0_CLKIN _L 1 L0 CLKIN H 0 L0 CLKIN L 0 Q CPUA HYPERTRANSPORT L0_CLKOUT_ L0_CLKOUT L0_CLKOUT_ L0_CLKOUT L0_CTLIN _H 1 L0 CTLIN L 1 L0 CTLIN H 0 L0 CTLIN L 0 L0_CADIN_H 15 L0_CADIN_L 15 L0_CADIN_H 14 L0_CADIN_L 14 L0_CADIN_H 13 L0_CADIN_L 13 L0_CADIN_H 12 L0_CADIN_L 12 L0_CADIN_H 11 L0_CADIN_L 11 L0_CADIN_H 10 L0_CADIN_L 10 L0_CADIN_H 9 L0_CADIN_L 9 L0_CADIN_H 8 L0_CADIN_L 8 L0_CADIN_H 7 L0_CADIN_L 7 L0_CADIN_H 6 L0_CADIN_L 6 L0_CADIN_H 5 L0_CADIN_L 5 .
